Broadcast station locator for a local area network

ABSTRACT

Method and apparatus for determining the location of a broadcasting station in a local area network communications system such as Ethernet that is arranged in a bus topology. An echo module, positioned at one end of a cable, receives a packet broadcast by a station and broadcasts a distinctive echo pulse on the cable during the interframe gap or at another chosen time. A processor module positioned at a second end of the cable receives the originally broadcast packet and the echo pulse, notes the times of receipt t 1  and t 2 , respectively, of these signals, and determines the temporal distance T 1  from the broadcasting station to the echo module by the equation 
     
         T.sub.1 =(t.sub.2 -t.sub.1 -Δt.sub.dp)/2, 
    
     where Δt dp  is a time delay associated with validation of the echo pulse.

TECHNICAL FIELD

This invention relates to local area networks and to apparatus fordetermining the location of each transmitting station in a local areanetwork.

BACKGROUND ART

Although a local area network ("LAN") communications system such asEthernet (trademark of the Xerox Corporation) allows a plurality oftransceivers to tap into the cable upon which the network relies, withrather generous limits on the maximum number of transceivers and thedistance of closest approach for such transceivers, it is necessary forsome purposes to determine with acceptable accuracy the location of eachbroadcasting transceiver on the cable. Frye, in U.S. Pat. No. 3,434,049,and Oliver et al., in U.S. Pat. No. 4,766,386, disclose the use of timedomain reflectometry techniques to determine whether a given cable has asubstantial impedance discontinuity, indicating the presence of a cableshort, an open cable or another similar problem with transmission ofsignals on the LAN cable. However, these techniques do not permit thedetermination of source identity and location, with acceptable accuracy,of a broadcasting station on the cable that is not associated with animpedance discontinuity.

It is an object of this invention to provide apparatus that can operatewithin the constraints imposed by an LAN system such as Ethernet andthat allows determination of location of each broadcasting transceiveron a cable in the network.

SUMMARY OF THE INVENTION

This object is met by the invention which provides, in one embodiment,two devices, to be positioned at opposite ends of a linear cable networkthat contains a plurality of broadcasting transceivers. It is assumedthat the LAN system has an interframe gap, similar to the 9.6-10.6microseconds ("μsec") time interval or gap associated with an Ethernetor similar system, during which no transceiver broadcasts a signal afterreceipt of the immediately preceding signal.

Assume that a transceiver or other broadcasting station has justbroadcast a signal in both directions on a cable 12, as illustrated inFIG. 1A; and assume that the location of this transceiver is not yetknown. The broadcast signal will propagate in both directions on thecable 12, as illustrated in FIG. 1B. The propagating signal is receivedby an echo module 11, positioned at one end of the cable 12, and an echopulse is broadcast by the echo module on the cable after a predeterminedpacket monitoring time interval of length Δt_(d) that is much less thanthe length of the interframe gap Δt_(gap). This rebroadcast occurs inthe interframe gap or quiet period that would ordinarily follow thereceipt of the propagating signal. Echo pulse broadcast may occur atother times as well.

The signal or packet originally broadcast by the transceiver is receivedby a processor module 13 at the other end of the cable 12, and the timet₁ at which the original signal arrives at the receiver-processor moduleis determined by this module. The echo pulse broadcast by the echomodule 11 then arrives at the processor module 13 at a time t₂, and thistime is determined by the processor module, with the same monitoringtime delay Δt_(d) included in t₁ and t₂. The length of the time intervalΔT₁ required for a signal to travel from the broadcasting transceiver tothe echo module is then determined by the relation ΔT₁ =(t₂ -t₁-Δt_(dp))/2, where Δt_(dp) is a net time delay associated with signalprocessing in the processor module. where Δt_(dp) is a time delayassociated with echo pulse validation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A, 1B and 1C illustrate broadcast of a packet by a station onto acable, propagation of this packet in both directions on the cable, andbroadcast of an echo packet at one end of the cable, according to theinvention.

FIG. 1D illustrates broadcast of a packet onto a cable by a stationpositioned on a branch of the cable.

FIG. 2 is a graphic view of the time line for receipt and broadcast ofthe packets shown in FIGS. 1A, 1B and 1C.

FIG. 3 is a block diagram illustrating the overall operation of thefunctional blocks that comprise the echo module that is positioned atone end of an LAN cable.

FIG. 4 is a block diagram illustrating some of the operations of thefunctional blocks that comprise the receiver-processor module that ispositioned at a second end of an LAN cable according to the invention.

FIGS. 5, 6 and 7 are schematic circuit diagrams of the echo module, theprocessor module, and the event timer control and event timer modulesthat comprise one embodiment of the invention.

FIG. 8 illustrates the use of two cables with the invention.

BEST MODE FOR CARRYING OUT THE INVENTION

With reference to FIG. 1A, a signal that is introduced onto a LAN cable12 by a broadcast station or transceiver that is tapped into the cable,will travel toward a first end of the cable and toward a second end ofthe cable as separate signals or packets BP, as illustrated in FIG. 1B.In one embodiment of the invention, an echo module 11 is positioned atone end of the cable 12, to receive the originally broadcast packet BPand to issue an echo pulse EP, as illustrated in FIG. 1C, after apredetermined monitoring time delay Δt_(d) at the echo module 11. Aprocessor module 13 positioned at a second end of the cable 12 receivesthe originally broadcast packet BP, notes the time t₁ of such receipt,receives the echo pulse EP and notes the time t₂ of such receipt, anddetermines the cable propagation time ΔT₁ from the broadcast station tothe echo module 13 approximately by the relation ΔT₁ =(t₂ -t₁-Δt_(dp))/2, where Δt_(dp) is a net time delay for processing in theprocessor module 13.

According to the Open Systems Interconnection ("O.S.I.") Standardproposed by Zimmerman in I.E.E.E. Trans. on Commun., vol. COM-28, 1980,pp. 425-432, and adopted by the O.S.I. Standards Committee, a local areanetwork may have as many as seven layers for message processing at eachstation. At the lowest level, called the physical layer, communicationbetween station and cable occurs in units of individual bits and/orbytes. The physical layer may include cables, connectors, voltage levelsensors and provision for particular signal generation and propagationstandards. In the next higher level, called the data link layer, signalsare exchanged by use of frames. A frame is a sequence of bytes,including a header that specifies source and destination of the frameand certain control and error check fields, plus the data to betransported. The next higher level, called the network layer, transportsinformation across the LAN in packets and is the "lowest" level thatrecognizes and works with the topology of the LAN. A packet may be acollection of frames, spaced apart by no more than a predeterminedamount on the LAN cable that carries the signals.

A local area network communication system such as Ethernet allows use ofa branching, non-rooted tree network or bus topology and limits themaximum station separation to about 0.5 kilometers at the physicallayer. In order to minimize or at least control packet collisions on theLAN, one of the constraints built into the system is that, after atransceiver has either received or transmitted a message or has sensed acollision of two packets, the transceiver must remain silent and notbroadcast for at least a minimum time interval of length Δt_(gap), gapcalled the interframe gap length. For a system such as Ethernet,Δt_(gap) =9.6-10.6 μsec, depending on the circumstances. Imposition ofsilence on the network for an interframe gap allows a signal that isreceived by a transceiver on the LAN to propagate to its destinationbefore another such signal is launched by a transceiver that earlierreceived this signal. Collisions of packets propagating on the LAN arenot avoided but are merely reduced in number by use of the interframegap.

The interframe gap time interval is used to advantage by the inventionto determine the position on the network, with reasonable accuracy, ofthe station that last broadcast a packet on the network. The interframegap time interval is used to propagate an echo pulse EP for thebroadcast packet BP received on the cable 12, from the echo module 11 tothe processor module 13; and formation of a simple difference in timesof arrival of the two signals at the module 13 is used to determine thedistance, expressed in signal propagation time, of the station thatbroadcast the "last" packet on the cable 12 from the echo module 11. Ifthe broadcasting station is positioned on a branch of the LAN networkthat intersects the "main" cable 12, on which the echo and processormodules 11 and 13 are located, at node point NP as shown in FIG. 1D,only the temporal distance ΔT₁ from this node point NP to the echomodule is determined by this technique. FIG. 2 graphically illustratesthe time line for receipt of the broadcast packet BP of the modules 11and 13 and broadcast of an echo pulse EP by the echo module 11.

FIG. 3 is a block diagram illustrating the major functional componentsof the echo module 11. A broadcast packet BP is received at an inputterminal of the echo module 11 as shown. The input terminal includes areceiver-amplifier module 21 that receives a broadcast packet BP as asequence of pulses and issues as an output signal a sequence ofapproximately square pulses having the same lengths, relativeseparations and relative positions as the pulses that comprise thebroadcast packet received as an input signal; each pulse that is part ofthe packet received is reformed as an approximately square pulse, andbroadcast packets with up to 20 dB of attenuation are recognized andreformed by the receiver-amplifier module 21. The receiver-amplifiermodule 21 should be capable of accurately reproducing signals with anassociated frequency of up to 10 MHz or the maximum operating frequencypermitted at the physical layer on the cable network, and the module 21should filter out or otherwise attenuate higher frequency cable noise.This filtering may be done by a standard arrangement of resistor andcapacitor in series with a capacitor bypass to ground, where thisresistor-capacitor circuit has an associated break frequency somewhereabove the maximum operating frequency.

The output signal from the receiver-amplifier module 21 is fed to apulse modifier module 23 (optional) that receives the sequence ofsquared pulses that comprise the reformed broadcast packet. The pulsemodifier module 23 issues a single pulse or sequence of pulses having afirst predetermined voltage v₁ and having a time interval of lengthΔt_(p1) =50 nanoseconds ("nsec"), each as an output signal, if at leastone square pulse is received at the input terminal, and issues a d.c.output signal of duration Δt_(p2) of a second predetermined voltage v₂if no square pulse is received at the input terminal of the module 23.One such pulse of temporal length Δt_(p1) is issued in response toreceipt of each pulse that is part of the packet, even though the timeinterval corresponding to the length of the broadcast packet BP may beless than 50 nsec. A pulse of temporal length 50 nsec is the minimumlength pulse that can travel through a series of delay lines withoutunacceptable loss of definition. If Manchester encoding of signals isused for the LAN, each bit of such a signal comprises two consecutivecomponents, a logical "zero" and a logical "one", each approximately 50nsec in length. Inclusion of the pulse modifier module 23 provides apulse of better definition.

The pulse modifier module 23 produces an output signal that is fed to anend-of-packet ("EOP") detector 25 as an input signal. If such inputsignal includes a pulse of temporal length 50 nsec and of voltage v₁,the EOP detector 25 issues as an output signal a pulse of a thirdpredetermined voltage v₃ of temporal length equal to a time intervalΔt_(p1) +Δt_(p2) =450 nsec; if the detector 25 does not receive anotherinput signal pulse with voltage v₁ within a time interval of lengthΔt_(p2) after the detector 25 receives the immediately preceding inputsignal, the output signal of the EOP detector 25 makes a transition to afourth predetermined voltage v₄. The output signal of the EOP detector25 will thus make a transition from the voltage v₃ to the voltage v₄only if a second pulse is not received by the detector 25 within a timeinterval of length Δt_(p2) =400 nsec after receipt of the precedingpulse; any time interval of length >200 nsec would probably sufficehere. For a communications system such as Ethernet, worst caseManchester encoding of signals produces a gap or time interval of lengthat most 200 nsec between successive positive edges of the data. Thecircuit used for the EOP detector 25 uses 400 nsec time separation as acriterion for absence of a next pulse, because the phase shift of thereceiver-amplifier module 21 can be as much as 50% on signals of varyingamplitude. For example, a shift in the d.c. level of thereceiver-amplifier module 21 may cause that module to "hiccup" for ashort period of time as it adjusts to the new d.c. bias level. Thethreshold length Δt_(p2) associated with the end-of-packet detector 25may be varied to take account of other network constraints on processingof data. If the pulse in the broadcast packet BP thus received by theecho module 11 is the "last" such pulse before an interframe gap, theEOP detector 25 will sense this and its output signal will be a pulse oflength Δt_(p1) +Δt_(p2) =450 nsec and of voltage v₃, followed by atransition to an unvarying voltage level v₄. If the pulse sensed in thebroadcast packet BP is not the last pulse received before an interframegap, the output signal of the EOP detector 25 will not make a transitionto the voltage level v₄ after a time interval of length 450 nsec.

The output signal of the receiver-amplifier module 21 is also receivedby a packet activity module 27 (optional) that counts the number of bitsN received in the broadcast packet input signal at the echo module 11and counts the number of packets M received. If the number N is at leastequal to a predetermined positive number N₁, the packet activity module27 issues a start-of-packet ("SOP") output signal of a fifthpredetermined voltage v₅ and resets N to zero; and if N<N₁, the moduleissues a SOP-absent output signal of a sixth predetermined voltage v₆,indicating that the signal received at the module 11 is not a packet,and resets N to zero. In practice, the number N₁ may be chosen to be 64or 128 or some similar number that distinguishes between the number ofbits contained in a genuine packet and the number of bits received in apacket fragment that might result from collision of two such packets. AnSOP output signal of voltage v₅ indicates that the echo module 11 isreceiving the start of a bona fide packet.

A packet counter within the packet activity module 27 receives andcounts the SOP signals. If the number M of such SOP signals received isat least equal to a second predetermined number M₂, and if N≦N₁, thepacket activity module 27 issues a transmitter control enable signalhaving a seventh predetermined voltage v₇ ; and if N<N₁ or M<M₂, orboth, the module 27 issues an output signal having an eighthpredetermined voltage v₈.

The packet counter is not required by the invention, but its inclusionallows the operator to avoid time delays associated with propagation ofthe echo packet BP and problems with signal repeaters, through controlof the number M₂. If M₂ is chosen to be 60, for example, an echo packetwill be issued by the echo module 11 at most once for every 60 broadcastpackets BP received from the plurality of broadcasting stations on theLAN. The SOP counter 27 can be effectively removed from the packetactivity module 27 by setting M₂ ≦1. The packet activity and countermodule 27 may be effectively deleted, for example by setting N₁ =1 or bydeleting the circuitry that performs the functions of the module 27.

A transmitter control module 31 receives the output signal from the EOPdetector 25 and the SOP output signal or the output signal from thepacket activity and counter module 27; and if the voltages associatedwith these two output signals have the levels v₄ and v₅ (or V₄ and V₇),respectively, the transmitter control module 31 issues a transmittercontrol output signal of a ninth predetermined voltage v₉ to enable atransmitter to issue an echo pulse EP. If the output signals of one ormore of the EOP detector 25 or the packet activity and counter module 27are not equal to v₄ or v₅, respectively, the transmitter control module31 issues a transmitter control output signal having a tenthpredetermined voltage v₁₀ that disables or does not activate thetransmitter. If the module 31 issues a transmitter enable signal, thismodule also issues a reset signal that is fed back to the packetactivity module 27 to reset the SOP counter number M to M=0.

The output signal from the transmitter control module 31 is received bya transmitter module 33; and if this output signal has the voltage levelv₉, the transmitter module 33 is enabled and broadcasts an echo pulse EPon the cable that is a single, constant-amplitude pulse having a lengthequal to a predetermined time length Δt_(p3), which may be chosen to beof the order of 1 μsec. From the time the front end of the broadcastpacket BP is received at the echo module 11 until the front end of theecho pulse EP is issued by the transmitter module 33 onto the cable, amonitoring delay time interval of length Δt_(d) approximately equal to455 nsec elapses; this temporal length is known to an accuracy of withintwo nsec. The echo pulse EP will travel down the cable 12 toward theprocessor module 13 during the interframe gap or at any time in anotherembodiment. When the echo pulse EP is received by the processor module13 at the other end of the cable 12, it is expected that no other packetor pulse will be present.

At the other end of the cable 12, the processor module 13 also receivesthe original broadcast packet BP from one of the broadcast stations thatis tapped into the cable 12. The input signal representing the broadcastpacket BP is passed through a receiver-amplifier module 41 thatfunctions identically to the receiver-amplifier module 21 for the echomodule 11. The output signal from the receiver-amplifier module 41 isthen passed to a pulse modifier module 43 (optional) that functionsidentically to the pulse modifier module 23 for the echo module 11. Thepulse modifier module 43 for the processor module 13 thus issues anoutput signal that is a pulse having a predetermined length Δt_(p4) =50nsec and having a predetermined voltage v₁₁, if at least one pulse isreceived by the module 43; and the module 43 issues a d.c. output signalhaving a predetermined voltage v₁₂ if no pulse is received at the module43. An end-of-packet detector 45, constructed similarly to the EOPdetector 25 for the echo module 11, receives the output signal from thepulse modifier module 43; and if the pulse received by the processormodule 13 is the last pulse before an interframe gap, the EOP detector45 will produce a single pulse of predetermined voltage v₁₃ havinglength Δt_(p4) +Δt_(p5), =450 nsec followed by transition to a d.c.signal having a predetermined voltage v₁₄.

A packet activity module 47 (optional), constructed similarly to thepacket activity module 27 but without the SOP counter, receives theoutput signal from the receiver-amplifier module 41 and counts thenumber of bits N received in the input signal. If the number N of bitsreceived by the pocket activity module 47 is at least equal to apredetermined positive number N₃, the packet activity module 47 issues astart-of-packet SOP output signal having a predetermined voltage v₁₅ ;and if N<N₃, the module 47 issues a SOP-absent output signal having apredetermined voltage v₁₆.

An echo detector 49 receives the output signal from thereceiver-amplifier module 41 and determines the single-pulse length ofthis output signal. If the pulse length exceeds a predetermined temporallength Δt_(p6) the echo detector 49 issues an echo-detected outputsignal having a predetermined voltage v₁₇ ; and if this pulse lengthdoes not exceed the length Δt_(p6), the echo detector 49 issues anecho-absent output signal having a predetermined voltage v₁₈. Thetemporal length Δt_(p6) may be chosen to be about 800 nsec if thetemporal length Δt_(p3) =1 μsec; in any event, Δt_(p6) is chosen to beless than but approximately equal to Δt_(p3).

Collisions of signals are part of the environment in which a transceiveror other station operates on an LAN of this type, and the processormodule 13 is provided with an optional collision detector 15 ofconventional design that receives each incoming broadcast packet. If aportion of one such packet is overlapped by a portion of another suchincoming packet, the collision detector 51 issues on output signalhaving a predetermined voltage v₁₉, indicating that a packet collisionis detected; if no packet collision is sensed by the module 51, thecollision detector 51 issues an output signal having a predeterminedvoltage v₂₀.

An event timer control module 53 receives as input signals the outputsignals of the EOP detector 45, the packet activity module 47, the echodetector 49 and the collision detector 51 and produces a first outputsignal of predetermined voltage v₂₁ if: (a) the EOP detector outputsignal for BP has a voltage equal to v₁₃ ; (b) the packet activity andcounter module output signal for BP has a voltage equal to v₁₅ ; (c) theecho detector module output signal has a voltage equal to v₁₈ ; and (d)(optional) the collision detector module output signal has a voltageequal to v₂₀ ; this indicates that a broadcast pulse has previouslyarrived at the processor module 13 and that this packet to arrive is EP,a bona fide echo pulse.

An event timer module 55 receives the event timer control output signaland resets to zero and activates an event timer at the time t₁ ofreceipt of an output signal of voltage V₂₁. The running of the timer inthe timer module 55 is stopped at a time t₂ at which the event timermodule 55 receives an event timer control module output signal ofvoltage V₂₂, or when the accumulated time exceeds a predeterminedmaximum time Δt_(max). The accumulated time Δt on the timer between thepoint at which the timer is reset and started, representing receipt ofBP, and the time at which the timer is stopped, representing receipt ofEP, is the difference Δt=t₂ -t₁ of times of arrival of the front ends ofthe broadcast packets BP and EP at the processor module 13 with the timedelay Δt_(d) incorporated in each of the times t₁ and t₂ by processingin the processor module 13. The distance, measured in signal propagationtime on the cable 12, from the station that broadcasts the packet BP andthe echo module 11 is then determined by the relation ΔT₁₌(Δt-Δt_(dp))/2.

FIG. 5 illustrates the major functional groupings of electroniccomponents and devices that comprise the echo module 11, according toone embodiment of the invention. The receiver-amplifier module 21comprises a high quality amplifier unit 100 that receives the inputsignal from the cable 12 through a capacitor 101 and a resistor 103,arranged in series at an input terminal of the amplifier 100. Theamplifier 100 is preferably chosen to amplify pulses having attenuationas much as 20 dB and to square each pulse so that the output signal fromthe amplifier 100 is a sequence of squared and amplified pulses thatotherwise replicate the sequence of pulses received at the inputterminal of the amplifier 100. An amplifier power supply 109 has astandard voltage V_(cc) such as 5 volts and is connected to the powersupply input terminal of the amplifier 100 through a resistor 105 thatmay have a resistance value of the order of 20 Ohms. The power inputterminal is also grounded through a capacitor 107 that may have a valueof the order of 100 nanofarads ("nf"). Any common emitter and commonbase terminals of the amplifier 100 are connected to ground through acapacitor 111 that may have a value of the order of 1 nf and are alsoconnected to the output terminal of the amplifier 100 through a resistor113 having a resistance value of the order of 3 kilo-ohms.

The pulse modifier module 23 (optional) receives the output signal ofthe receiver-amplifier module 21 through a resistor 115 having aresistance value of the order of 50 Ohms, and this signal is passed tothe input terminal of a time delay module 117 that produces an outputsignal that is a replica of the input signal but delayed by a timeΔt_(p1) =50 nsec.

The input signal to the time delay module 117 is also fed to the inputterminal of a first flipflop 119. Each flipflop used herein is assumedto have a data input terminal D, a clock input terminal CLK, a presetinput terminal PR, a clear input terminal CLR, and two output terminalsfor logically complementary output signals Q and Q*. The flipflop 119has its D input terminal held high by connection directly to the powersupply 109, and its clock input terminal CLK receives the input signaldelivered to the time delay module 117. A second flipflop 121 also hasits D input held high by direct connection to the power supply 109, andits clock input terminal CLK receives the output signal, with theassociated time delay of Δt_(p1) =50 nsec, from the time delay module117. The Q* output terminal of the flipflop 121 is connected to theclear input terminal CLR of the flipflop 119; and the Q output terminalof the flipflop 119 is connected to the clear input terminal CLR of theflipflop 121 and also serves as the source of the output signal of thepulse modifier module 23. The two clock input terminals CLK of theflipflops 121 and 119 each receive a pulse, with the two pulses beingdisplaced by a time interval of length Δt_(p1) =50 nsec from oneanother; and the Q* output signal from the flipflop 121 is used to clearthe flipflop 119. The result is a pulse of temporal length Δt_(p1) =50nsec at the Q output terminal of the flipflop 119, if the input signalto the pulse modifier module 23 has a temporal length of any amount thatcan be sensed by the flipflops and 121.

The EOP detector module 25 includes one or more multi-tap time delaymodules that produce a plurality of output signals that are time delayedrelative to one another by approximately 25 nsec or an integral multiplethereof. A sequence of such time delayed output signals is produced witha maximum time delay of Δt_(p2) =400 nsec as indicated; again, anyΔt_(d2) >200 nsec would probably suffice here. In the embodiment shownin FIG. 5, two time delay modules 123 and 125, each providing up to 250μsec time delay, are used together to produce the desired set of 17 timedelayed signals with associated time delays 0, 25, 50, . . . , 400 nsec.The output signals from the time delay module or modules are fed to alogical summing means 127, whose output signal is thus a single pulse oftemporal length Δt_(p1) +Δt_(p2) =450 nsec. At the end of this pulse,the output signal changes to a different voltage unless another inputsignal to the EOP detector module 25 has been received within a timeinterval of length Δt_(p2) =400 nsec after receipt of the immediatelypreceding pulse.

Under a worst case Manchester encoding circumstance on Ethernet at 10MHz, successive positive edges of the incoming data would be separatedby at most 200 nsec; and a pulse stand-off time of Δt_(p2) =400 nsec isused here to compensate for possible degradation of signals. If noincoming pulse follows another incoming pulse within 200 nsec in time,it is assumed that the present pulse is the last pulse of a packetreceived by the echo module 11; and the result of this is that theoutput signal from the EOP detector module 25 is a pulse of lengthΔt_(p1) +Δt_(p2) =450 nsec, followed by a transition to a differentvoltage level.

The packet activity and counter module 27 (optional) includes amonostable vibrator 129, with a first input terminal receiving theoutput signal from the end-of-packet detector 25. The vibrator 129 has asecond input terminal and a clear input terminal CLR that are directlytied to the power supply 109. A fourth input terminal REX/CEX of thevibrator 129 is connected to the power supply 109 through a resistor 131having resistance of the order of 5 kilo-ohms; and a fifth inputterminal CEX of the multi-vibrator 129 is connected to the power supply109 through a series combination of the resistor 131 and a capacitor 133that has a capacitance value of the order of 0.4 nf. The vibrator 129will clear itself after a time interval of approximately 0.8 μsec.

As used herein, a monostable vibrator is an analog device having first,second and clear input terminals, fourth and fifth control inputterminals denoted REX/CEX and CEX, two output terminals denoted Q and Q*that produce logically complementary output signals, and a power supplyterminal denoted Vcc. An example of such a vibrator is the 74LS123retriggerable monostable vibrator sold by Motorola. In one mode of use,the input terminals second, clear, fourth and fifth are connecteddirectly or indirectly to the power supply so that an internal RCcircuit provides the length of the retriggering time interval. However,a resistor of resistance value RE may be connected between the REX/CEXterminal and the power supply, and a capacitor of capacitance value CEtogether with this resistor may be connected in series between the CEXterminal and the power supply; and the time constant τ associated withthe retriggering time interval then becomes an adjustable parameter,viz.

τ=K(RE)(CE), where K is a numerical constant, equal to approximately0.45 for the Motorola 74LS123 vibrator.

The multi-vibrator 129 has two output terminals, and the Q* outputterminal is connected to the CLR input terminal of a first ripplecounter 135 that produces a single output pulse when the count N of thecounter reaches a predetermined positive integer N₁. The clock inputterminal CLK of the counter 135 receives the output signal from the EOPdetector module 25, or from the amplifier-receiver module 21. The outputsignal of the counter 135 is fed to the clock input terminals CLK ofeach of two flipflops 137 and 139, and the Q output terminal of thevibrator 129 is connected to the clear input terminals CLR of each ofthese two flipflops. The D input terminal of the first flipflop 137 isconnected directly to the power supply 109, and the D input terminal ofthe second flipflop 139 receives a signal from another source not yetdiscussed. The Q output terminal of the first flipflop 137 is connectedto the clock input terminal CLK of a second ripple counter 141, which isassumed to produce a pulse at the output terminal thereof when the countM of this second counter reaches a second predetermined positive integerN₂. The output terminal of the second counter 141 is connected to the Dinput terminal of the second flipflop 139. The output signal issued bythe Q* output terminal of the second flipflop 139 serves as the outputsignal from the packet activity module 27.

In an embodiment of the invention in which the number M of packetsreceived is not counted, the first flipflop 137 and the second counter141 would be deleted and the D input terminal of the second flipflop 139would be connected to the power supply 109, either directly or through aresistor (optional) as shown for the flipflop 227 that is a part of thepacket activity and counter and module 47 for the processor module 13 inFIG. 6.

The transmitter control module 31 comprises a flipflop 141 and twomonostable vibrators 143 and 151, connected as follows. The D inputterminal and the clock input terminal of the flipflop 141 receive theoutput signals from the packet activity and counter module 127 and theend-of-packet detector 25, respectively, and the Q* output terminal ofthis flipflop issues the EOP detector output signal.

The second input and clear input terminals of a first monostablevibrator 143 are connected to ground through a capacitor 145 that has acapacitance value of the order of 10 μf and are connected to the supply109 through a resistor 146 (optional) that has a resistance value of theorder of 5 kilo-ohms. A fourth input terminal of the vibrator 143 isconnected to the power supply 109 through a resistor 147 that has aresistance value of the order of 70 kilo-ohms; and a fifth inputterminal is connected to the power supply 109 though a seriescombination of the resistor 147 and a capacitor 149 having a capacitancevalue of the order of 1 nf. The Q* output terminal of the vibrator 143is connected to the preset input terminal PR of the flipflop 141. Thevibrator 43 will clear itself after a time interval Δt_(v) of about 30μsec so that this part of the circuit is available to analyze anotherpacket; in practice, any choice Δt_(v) >10 μsec would probably sufficehere.

A first input terminal of the second monostable vibrator 151 isconnected to ground, and the second input and clear input terminalsthereof are connected to the power supply 109. A fourth input terminalof the vibrator 151 is connected to the power supply through a resistor153 having a resistance value of the order of 20 kilo-ohms; and a fifthinput terminal is connected to the power supply 109 through a seriescombination of the resistor 153 and a capacitor 155 having a capacitancevalue of the order of 0.1 nf. The vibrator 151 will clear itself after atime interval of about 0.9 μsec. The Q output terminal of the vibrator151 is connected to the first input terminal of the vibrator 143, andthe Q* output terminal of the vibrator 151 is connected to the clearinput terminal CLR of the flipflop 141. The Q output signal from theflipflop 141 is also connected to the clear input terminal CLR of thesecond counter 141 of the packet activity module 27 so that this Q*output signal serves as a reset signal for the packet activity module 27and as the output signal for the transmitter control module 31 thatenables the transmitter module 33.

The transmitter module 33 receives the output signal from thetransmitter control module 31, and this signal is passed through a firstresistor 161 (optional) having a resistance value of the order of 500Ohms to the base of an npn transistor 163 whose emitter is grounded. Thebase of the emitter 163 is connected to ground through a second resistor165 (optional) that has a resistance value of the order of 500 Ohms. Thecollector of the transistor 163 is connected to the end of the cable 12through a series combination of a resistor 167 having a resistance valueof the order of 30 Ohms and a diode 167 (optional) whose anode isconnected to the end of the cable 12. The transmitter module 33 can beimplemented in many other ways as well. This completes the discussion ofthe embodiment of the echo module 11 shown in FIG. 5.

FIG. 6 illustrates the major functional groupings of electroniccomponents and devices that comprise the receiver-processor module,except the collision detector 51, which is conventional and well knownin the art, the event timer control module 53, and the event timermodule 55.

The amplifier-receiver module 41 in the receiver-processor module 13includes an amplifier 171 that amplifies signals that are attenuated upto 20 dB and squares any pulse received so that the output signal fromthe amplifier 171 is a sequence of squared pulses with temporal lengthsand separations between consecutive pulses that are substantially thoseof the sequence of input pulses received in the module 41. The amplifier71 receives the input signal from the end of the cable 12 through acapacitor 173 having a value of the order of 0.1 μf and a resistor 175(optional) having a resistance value of the order of 100 Ohms. A commonemitter terminal and a common base terminal, if any, of the amplifierare connected to ground through a capacitor 177 that may have a value ofthe order of 1 nf. A high voltage power supply 179 is connected to thepower supply terminal of the amplifier 171 through a resistor 181(optional) having a resistance value of the order of 20 Ohms, and thepower supply input terminal is also connected to ground through acapacitor 183 having a capacitance value of the order of 1 nf. Theoutput terminal of the amplifier 171 issues the receiver-amplifiermodule output signal, and this output terminal is also connected toground through the capacitor 177.

The receiver-amplifier module output signal is passed through a resistor197 (optional) having a resistance value of the order of 50 Ohms to aninput terminal of a multi-tap time delay module 189 that provides a 50nsec time delay and is part of the pulse modifier module 43 (optional).The output signal from the module 41 is also passed to the clock inputterminal CLK of a first flipflop 197, and the output signal of the timedelay module 189 with associated time delay 50 nsec is passed to theclock input terminal CLK of a second flipflop 199. The D input terminalsof the two flipflops 197 and 199 are both directly connected to thepower supply 179 so that receipt of a clock pulse automatically causesissue of a pulse. The Q output terminal of the flipflop 199 is connectedto the clear input terminal CLR of the flipflop 197, and the Q outputterminal of the flipflop 197 is connected to the clear input terminalCLR of the flipflop 199 and also serves as a source of the output signalfrom the pulse modifier module 43. The output signal from the module 43is again a pulse of temporal length Δt_(p4) =50 nsec.

This first output signal of the pulse modifier module 43 is received bythe end-of-packet detector 45 at the input terminal of a multi-tap timedelay module that is part of the EOP detector 45. As shown in theembodiment of FIG. 6, the time delay module for the EOP detector 45 maycomprise two time delay modules 201 and 202 in a combination thatprovides time delayed output signals with associated time delays of 25nsec increments from 0 nsec, up to 400 nsec. The time delayed outputsignals are collectively fed to a logical summing means 203 whose outputterminal is connected to the clock input terminal of a flipflop 205.

The D input terminal, the preset input terminal PR and the clear inputterminal CLR of the flipflop 205 receive signals from sources not yetdiscussed, and the Q* output terminal provides the EOP detector outputsignal for the module 45. The Q output terminal of the flipflop 205 isconnected to a first input terminal of a first monostable vibrator 207,which has second input and clear input terminals connected to the powersupply 179. A fourth input terminal of the vibrator 207 is connected tothe power supply 179 through a resistor 209 having resistance value ofthe order of 5 kilo-ohms; and a fifth input terminal 211 is connected tothe power supply 179 through a series combination of the resistor 209and a capacitor 211 having capacitance value of the order of 0.1 nf. Thevibrator 207 will clear itself after a time interval of about 0.2 μsec.The Q* output terminal of the first monostable vibrator 207 is connectedto the clear input terminal CLR of the flipflop 205 and to a secondinput terminal of a second monostable vibrator 213 whose first inputterminal is grounded. The clear input terminal of the vibrator 213 isconnected to the power supply 179; a fourth input terminal is connectedto the power supply 179 through a resistor 215 having a resistor valueof about 100 Ohms; and a fifth input terminal is connected to the powersupply 179 through a series combination of the resistor 215 and acapacitor 217 having a capacitance value of the order of 1 nf. Thevibrator 213 will clear itself after a time interval of about 0.1 μsec.The Q* output terminal of the vibrator 213 is connected to the presetinput terminal PR of the flipflop 205. The vibrator 213 will clearitself after a time interval of about 54 μsec, in order to re-enablethis part of the circuit to analyze another incoming pulse.

The packet activity and counter module 47 (optional) includes a ripplecounter 219 and a monostable vibrator 221 that receive the output signalfrom the pulse modifier module 43, or from the receiver-amplifier module41, at the clock input terminal and first input terminal, respectively,of the counter 219 and vibrator 221. The second input and clear inputterminals of the vibrator 221 are connected directly to the power supply179. A fourth input terminal of the vibrator 221 is connected to thepower supply 179 through a resistor 223 having a resistance value of theorder of 5 kilo-ohms; and a fifth input terminal of the vibrator 221 isconnected to the power supply 179 through a series combination of theresistor 223 and a capacitor 215 having a capacitance value of the orderof 1 nf. The vibrator 221 will clear itself after a time interval ofabout 2.25 μsec. The Q* output terminal of the vibrator 221 is connectedto the clear input terminal CLR of the counter 219; and the Q outputterminal provides the output signal of the packet activity module 227.The ripple counter 219 issues a pulse at its output terminal when thecount N of pulses received directly or indirectly from thereceiver-amplifier module 41 exceeds a third predetermined number N₃,which may be of the order of 60-130.

The output terminal of the counter 219 is connected to the clock inputterminal CLK of a flipflop 227 whose D input terminal and preset inputterminal PR are connected to the power supply 179 through a resistor 229(optional) having a resistance value of the order of 5 kilo-ohms. Theclear input terminal CLR of the flipflop 227 is connected to the Qoutput terminal of the monostable vibrator 221. The Q* output terminalof the flipflop 227 is connected to the D input terminal of the flipflop205. The Q output terminal of the vibrator 221 issues the output signalof the packet activity detector 47.

The echo detector module 49 includes a multi-tap time delay module 189,an AND gate 195, a monostable vibrator 231 and a flipflop 233; the echodetector output signals control the reaction of the remainder of theprocessor module 13. The output signals from the time delay module 189are passed through the AND gate 195; and the output signal thereof, withassociated time delay Δt_(dp) ≈250 nsec, is passed to the second inputterminal of a monostable vibrator 231 whose first input terminal isgrounded. A clear input terminal of the vibrator 231 is connected to thepower supply 179; a fourth input terminal is connected to the powersupply 179 through a resistor 235 having a resistance value of about 5kilo-ohms; and a fifth input terminal is connected to the power supply179 through a series combination of the resistor 235 and a capacitor 237having a capacitance value of about 0.4 nf. The vibrator 231 will clearitself after a time interval of about 800 nsec. The Q* output terminalof the vibrator 231 is connected to the clock input terminal CLK of aflipflop 233 whose clear input terminal CLR receives the output signalfrom the packet activity module 47. The output signal from the AND gate195 provides a first output signal from the echo detector module 49,indicating that the candidate pulse received from the cable 12 by way ofthe module 41 is at least 250 nsec in length. This output signal is alsofed to the D input terminal of the flipflop 233, and the Q outputterminal thereof issues a second output signal from the module 49,indicating that the candidate pulse is at least 800 nsec in length andthat a "true" echo packet has arrived.

The details of the event timer control module 53 and the event timermodule 55, together with certain features that are not a part of theinvention, are illustrated in FIG. 7. The output signal from the EOPdetector 45 and a processor module enable signal SUREN are received attwo input terminals of an AND gate 251, and the output signal thereof ispassed to the input terminal of a two-input OR gate 252 (optional) thatreceives at its second input terminal a signal indicating that the databeing received and analyzed for some other process are valid. The datavalid signal could, for example, be generated by analysis of datareceived and analyzed by a time domain reflectometer ("TDR") that mayoperated in parallel with the invention for purposes of determining theexistence of one or more impedance discontinuities on the cable 12; theuse of TDR data or other similar data is not a part of the inventiondisclosed and claimed here, but provision is made for such additionaldata inputs in order to broaden the scope of possible applications ofthe invention. The output signal from the OR gate 252 is received by theclock input terminal CLK of a flipflop 253 whose D input terminal isconnected to the power supply 179. The preset and clear terminals PR andCLR, respectively, receive input signals from sources not yet discussed.The first echo detector output signal, received from the AND gate 195illustrated in FIG. 6, and the processor enable signal SUREN arereceived at two inputs of an AND gate 255 whose output signal is passedto the clock input terminal CLK of each of two or more flipflops 256 and257. The D input terminal of each flipflop 256 and 257 is connected tothe power supply 179 through a resistor 258 (optional) having aresistance value of about 1 kilo-ohm, and the clear input terminal CLRof each of these flipflops is connected to the Q* output of the flipflop253 for clearing after a packet has been analyzed. The preset inputterminal PR of each of the flipflops 256 and 257 may receive an inputsignal from another control source, such as a TDR, that is not a part ofthe invention. The Q* output terminal of the flipflop 256 (optional)issues an output signal indicating that some other condition such asabsence of a packet collision, is met or not met; the flipflop 257 maybe deleted if no other condition is required in order to initiate timingof the interval between arrival of two packets such as BP and BP at theprocessor module 13.

The Q* output terminal of the flipflop 257 issues an output signalindicating that an echo packet has been received and that the processormodule 13 is enabled to respond; and this output signal fed to inputterminals of an AND gate 261. The AND gate 261 may also receive one ormore Q* output control signals from one or more flipflops 256 indicatingthe presence of other conditions such as detection of an open cable ordetection of a short on the cable in a TDR interrogation of the cable12.

The output signal from the AND gate 261 is passed to the D inputterminal of a flipflop 263 whose clock input terminal CLK receives aperiodic clock signal from an oscillator 265 that produces an outputfrequency of 25 MHz and a period of length 40 nsec. The preset and clearinput terminals PR and CLR of the flipflop 263 are held at predeterminedvoltages VPR and VCLR so that the Q and Q* output signals of theflipflop 263 are controlled by what appears at the D input terminalthereof. The Q and Q* output terminals of the flipflop 263 produce thestart signal and the stop signals, respectively, for the event timermodule 55, corresponding to arrival of the broadcast packet BP and ofthe echo pulse EP.

The output signal from the AND gate 261 is also fed to a multi-tap timedelay module 275 that produces a signal with a sequence of associatedtime delays 5 nsec, 10 nsec, 15 nsec, . . . , 40 nsec, output signalsfrom the time delay module 275 have delay times of 5-40 nsec and are fedto eight input terminals of an octal D-type flipflop 277. These eightinput signals to the flipflop assembly 277 are inverted in order and fedto eight input terminals of a second octal D-type flipflop 279 as shownin FIG. 7. The clock input terminal of the flipflop assembly 277receives the stop time output signal from the Q* output terminal of theflipflop 263 so that from one to eight consecutive flipflops of thisassembly may have non-zero contents at the time the clock pulse isreceived, and these contents are issued as output signals. In a similarmanner, the clock input terminal CLK of the flipflop assembly 279receives the start time output signal from the Q-output terminal of theflipflop 263; and from one to eight consecutive input terminals of thisassembly may have non-zero contents that are issued as output signalswhen the start time clock pulse is received. The eight output signalsfrom the flipflop assembly 277 are received by eight input terminals ofa priority encoder 281 that converts the decimal number represented bythe eight input signals to a binary-coded number on three outputterminals thereof. In a similar manner, the eight output terminals ofthe flipflop assembly 279 are received by eight input terminals of asecond priority encoder 283 that issues a binary-coded output signal atthree output terminals thereof. The three binary-coded output signalsfrom each of the two priority encoders 281 and 283 are received by sixinput terminals of a 3×3 adder 285 having a four-bit binary output forfull addition, with a fifth output terminal provided for a carry bit.The output signals from the adder 285 represent a binary-coded valuecorresponding to time increments of 0, 5, 10, 15, . . . , 75 nsec, whichcorrespond to the 2⁴ =16 possible output values of the adder 285.

The four output terminals I1, I2, I3 and I4 of the adder 285 contain allavailable information on the "fine" component of the time intervallength T₁ ; that is, with an integer F defined by F=8.I4+4.I3+2.I2+1.I1,the "fine" component of T₁ is defined by ΔT₁ (fine)=F . (5 nsec) and isthus graduated in increments of 5 =l nsec. The quantity ΔT₁ (fine)represents the sum of the two fragments of the time interval length ΔT₁outside the "whole" 40 nsec time intervals defined by the clock pulsesource 265.

The start timer signal that issues from the flipflop 263 is also fed toa first counter enable input terminal ENP of each of two module 16counters 291 and 293. The four input input terminals of each of thecounters 291 and 293 and a second counter enable input terminal ENT of291, are held high.

The carry out output terminal Co of the counter 291, which issues apulse each time the counter 291 cycles from 15 to 0 modulo 16, isconnected to a second counter enable terminal ENT of the second modulo16 counter 293. The two counters 291 and 293 each receive a clock pulsefrom the 25 MHz. clock pulse source 265 a clock pulse every 40 nsec. Theresult of this is that, after the event timer module 55 has been startedby arrival of the broadcast packet BP and has been stopped by arrival ofthe echo pulse EP, the combined output signals from the two counters 291and 293 contain a count of the integer number C (0>C>255=2⁸ -1) of"whole" clock intervals, each of temporal length 40 nsec, that arecontained in the time interval of length T₁. Otherwise expressed,##EQU1## where [x] denotes the integral part of the real number x, thelargest integer that is ≦x. The number ΔT₁ (coarse)=C.(40 nsec) is the"coarse" component of ΔT₁, and the entire length ΔT₁ is expressible as##EQU2## where Δt_(dp) is the net time delay introduced by the processormodule.

Various features can be added to the invention as disclosed here. Asnoted above, a collision detection module 51 as in FIG. 4 can beoptionally included. A time domain reflectometer can be operatedtogether with the processor module 13 to locate positions on the cable12 where the cable impedance is substantially discontinuous,corresponding to the existence of a cable .he short, or a cable break oropen, or some other malady. The invention may even include a sourceaddress identifier, of conventional design, to identify the source orstation number of the station that has just broadcast the "lost" packetthat has caused an echo pulse EP to be issued.

The echo pulse need not be issued during the interframe gap timeinterval but can be issued at other times as well. However, in such anembodiment the use of a packet collision detector as part of theprocessor module 13, and use of a carrier sense circuit a part of theecho module 11, is probably required as the chance of a collision withthe echo packet is increased where this embodiment is used.

The invention may also be used in an embodiment in which the broadcastpulse arrives on the LAN cable 12 and the echo pulse is broadcast on aseparate, dedicated cable 14 that extends from the echo module 11 to theprocessor module 13, as illustrated in FIG. 8. Use of a separate cablewould allow deletion of all of the echo detector circuitry on theprocessor module. Within the processor module 13, the incoming echopulse EP would be fed directly to the event timer module.

I claim:
 1. Apparatus for determining the position of each of aplurality of transmitter-receiver stations that are connected to andcommunicate with each other on a bus topology cable network of suchstations by broadcasting and receiving packets on the cable, where if apacket is transmitted or received by a station, the station does notbroadcast a packet during an interframe time interval of predeterminedlength Δt_(gap) that immediately follows transmission or receipt of thepreceding packet, the apparatus comprising:an echo module, positioned ata first end of a cable, to receive a broadcast packet, to determinewhether a pulse in the packet is the last pulse received before aninterframe time interval and whether at least a predetermined number ofbroadcast packets have been received, and if both these conditions aresatisfied to broadcast an echo pulse on the cable network after apredetermined time delay Δt_(d) where Δt_(d) <<Δt_(gap) ; and aprocessor module, positioned at a second end of the cable, to receive abroadcast packet, to determine the time t₁ at which the broadcast packetarrives at the processor module, to receive an echo pulse signal, todetermine the time t₂ at which the echo pulse arrives at the processormodule, and to determine the time interval ΔT₁ required for a signal totravel from the broadcasting station to the echo module by the relationΔT₁ =(t₂ -t₁ -Δt_(dp))/2, where Δt_(dp) is a net time delay associatedwith signal processing in the processor module.
 2. Apparatus accordingto claim 1, wherein said echo module comprises:a receiver-amplifiermodule to receive a broadcast packet as a sequence of one or morepulses, to amplify and reform each pulse as a squared pulse, and toissue this sequence of squared pulses as an output signal; anend-of-packet detector to receive the receiver-amplifier module outputsignal as an input signal and to issue as an output signal a pulse oflength Δt_(p2) of a predetermined voltage v₃, where Δt_(p2) is apredetermined time interval length, and, if this detector does notreceive another non-zero input signal within a time interval of lengthΔt_(p2) after the detector receives the immediately preceding inputsignal, the output signal of this detector makes a transition to apredetermined voltage v₄ ; a packet activity and counter module toreceive the output signal from the receiver-amplifier module, to countthe number N of bits received in this signal, if the number of bitsreceived is at least equal to a first predetermined number N₁ to issue astart-of-packet output signal of a predetermined voltage v₅, and if N<N₁to issue a start-of-packet output signal of a predetermined voltage v₆ ;a transmitter control module to receive the output signals from theend-of-packet detector module and from the packet activity and countermodule, when these signals have voltages equal to v₄ and v₅,respectively, to issue an output signal of a predetermined voltage v₉ asan output signal, and when at least one of the output signals from theend-of-packet detector module or from the packet activity and countermodule does not have a voltage equal to v₄ or v₅, respectively, to issuean output signal of a predetermined voltage v₁₀ ; and a transmittermodule to receive the transmitter control module output signal and, whenthis signal has a voltage equal to v₉, to issue said echo pulse on saidcable.
 3. Apparatus according to claim 2, further comprising:a pulsemodifier module to receive said receiver-amplifier module output signal,to issue an output signal to said end-of-packet detector that is asingle pulse of a predetermined voltage v₁ and of length equal to apredetermined time interval Δt_(p1) if a non-zero input signal isreceived, and to issue an output signal of predetermined length Δt_(p2)to said end-of-packet detector that is a substantially constant,predetermined voltage v₂ if no non-zero input signal is received. 4.Apparatus according to claim 3, wherein said predetermined time intervallength Δt_(p2) is greater than 200 nsec.
 5. Apparatus according to claim3, wherein said pulse modifier module comprises:first and second signalpropagation lines to receive and propagate said receiver-amplifiermodule output signal, where the second signal line introduces a timedelay of said predetermined amount Δt_(p1) relative to the first signalline; and first and second flipflops, each having a data input terminaland a clock input terminal, whose data input terminals are held at highvoltages, with the first and second signal lines being connected to theclock input terminals of the first and second flipflops, respectively,where the Q* output terminal of the second flipflop is connected to theclear input terminal of the first flipflop, and the Q output terminal ofthe first flipflop issues said output signal from said pulse modifiermodule and is connected to the clear input terminal of the secondflipflop.
 6. Apparatus according to claim 3, wherein said end-of-packetdetector comprises:a delay line module having an input terminal toreceive said pulse modifier module output signal and having a pluralityof K consecutive time delay output terminals where AK is a positiveinteger, and each delay line module reproduces the input signal with apredetermined time delay Δt_(c) relative to the output signal from theimmediately preceding time delay output terminal, where Δt_(c) <Δt_(p1)and KΔt_(c) ≧t_(p2) ; and logical summing means for receiving the outputsignals from delay line module output terminals, for forming the logicalsum of these signals and for issuing this logical sum of said outputsignal of said end-of-packet detector module.
 7. Apparatus according toclaim 3, wherein said packet activity and counter module comprises:amonostable vibrator having a first input terminal to receive said pulsemodifier module output signal, having a second input terminal and aclear input terminal connected to a high voltage source, having a Qoutput terminal to issue an output signal pulse of predeterminedtemporal length Δt_(v) each time a pulse is received at the inputterminal, and having a Q* output terminal; a pulse counter having aninput terminal connected to the Q* output terminal of the monostablevibrator and having a clock input terminal connected to receive saidpulse modifier module output signal, where the pulse counter has anoutput terminal that issues a counter output signal that is a pulse andthat resets to zero each time the counter reaches a count N≧N₄, where N₄is a predetermined positive number; and a flipflop, having data inputand preset input terminals that are connected to a high voltage source,having a clock input terminal that receives the counter output signal,having a flipflop clear terminal that is connected to the Q outputterminal of the monostable vibrator, and having a Q* output terminalthat issues said start-of-packet output signal.
 8. Apparatus accordingto claim 7, wherein said predetermined temporal length Δt_(v) isapproximately 0.8 μsec.
 9. Apparatus according to claim 7, wherein saidpacket activity and counter module receives and counts the number M ofsaid start-of-packet output signals of said predetermined voltage V₅, ifM is at least equal to a second predetermined positive number N₂ saidmodule resets the number M to zero and issues a packet count outputsignal of a predetermined voltage V₉, and if M<N₂ said module issues apacket count output signal of a predetermined voltage V₁₀.
 10. Apparatusaccording to claim 9, wherein said packet activity and counter modulefurther comprises:a second flipflop, having data input and preset inputterminals that are connected to a high voltage, having a clock inputterminal that is connected to said first counter output terminal, havinga clear input terminal that is connected to said Q output terminal ofsaid monostable vibrator, and having a Q* output terminal; and a secondpulse counter having a clock input terminal connected to the Q outputterminal of the second flipflop and having a clear input terminal thatreceives a clear input signal from an external source, where the secondcounter has an output terminal that is connected to said data inputterminal of said first flipflop and that issues a second counter outputsignal that is a pulse and that resets to zero each time the secondcounter reaches a count L, where L is a predetermined positive integer.11. Apparatus according to claim 3, wherein said transmitter controlmodule comprises:a flipflop having a data input terminal to receive saidpacket activity and counter module output signal, having a clock inputterminal to receive said end-of-packet detector output signal, andhaving a preset input terminal, a clear input terminal and a Q* outputterminal, to issue a transmitter enable signal at the Q* outputterminal; a first monostable vibrator having a first input terminal thatis grounded, having a second input terminal and a clear input terminalconnected to a high voltage source, having a Q output terminal to issuean output signal pulse of predetermined temporal length Δt_(v1) eachtime a pulse is received at the first input terminal, and having a Q*output terminal that is connected to the clear input terminal of theflipflop; a second monostable vibrator having a first input terminalconnected to the Q output terminal of the first monostable vibrator,having a second input terminal and a clear input terminal connected to ahigh voltage source, and having a Q* output terminal connected to thepreset input terminal of the flipflop to produce an output signal pulseof predetermined temporal length Δt_(v2) each time a pulse is receivedat the first input terminal.
 12. Apparatus according to claim 11,wherein said predetermined temporal length Δt_(v1) is approximately 0.9μsec.
 13. Apparatus according to claim 11, wherein said predeterminedtemporal length Δt_(v2) is at least 10 μsec.
 14. Apparatus according toclaim 3, wherein said transmitter module comprises:a transistor with itsemitter grounded and its base connected to ground through a resistor andpositioned to receive said transmitter control module output signal; adiode with its cathode connected to the transistor collector and itsanode connected to said first end of said cable.
 15. Apparatus accordingto claim 1, wherein said processor module comprises:a receiver-amplifiermodule to receive a broadcast packet as a sequence of one or morepulses, to amplify and reform each pulse as a squared pulse, and toissue this sequence of squared pulses as an output signal; anend-of-packet detector to receive the receiver-amplifier module outputsignal as an input signal, to issue as an output signal a pulse of apredetermined voltage V₁₃ and of length equal to a predetermined timeinterval Δt_(p5), where Δt_(p5) is a second predetermined time intervallength, and, if this detector does not receive another non-zero inputsignal within a time interval of length Δt_(p5) after the detectorreceives the immediately preceding input signal, the output signal ofthis detector makes a transition to a predetermined voltage v₁₄ ; apacket activity and counter module to receive the output signal from thereceiver-amplifier module, to count the number N of bits received inthis signal, if N is at least equal to a predetermined positive numberN₃ to issue a start-of-packet output signal of a predetermined voltagev₁₅, and if N<N₃ to issue start-of-packet output signal of apredetermined voltage v₁₆ ; an echo detector to receive thereceiver-amplifier module output signal and determine the pulse lengthof this signal, where, if the pulse length exceeds a predeterminedlength Δt_(p6), the echo detector issues an output signal of apredetermined voltage v₁₇, and if the pulse length does not exceed thelength Δt_(p6), the echo detector issues an output signal ofpredetermined voltage v₁₈ ; an event timer control module to receive asinput signals the output signals of the end-of-packet detector, thepacket activity and counter module, the echo detector, to produce atimer control output signal of predetermined voltage v₂₁ if (a) theend-of-packet detector output signal for a first signal has a voltageequal to v₁₃ for said broadcast packet, (b) the packet activity andcounter module output signal for the first signal has a voltage equal toV₁₅ for said broadcast packet, and (c1) the echo detector output signalfor a succeeding signal has a voltage equal to v₁₈, and to produce atimer control output signal of predetermined voltage v₂₂ if conditions(a), (b) are satisfied and (c2) the echo detector output signal for thesucceeding signal has a voltage equal to V₁₇ ; an event timer module toreceive output signal from the event timer control module, to reset tozero and initiate a timer with arrival of a timer control output signalof voltage V₂₁, to stop the timer and determine the accumulated time Δtindicated on the timer with arrival of a timer control output signal ofvoltage V₂₂, to stop and clear the timer if the accumulated time Δtexceeds a predetermined time Δt_(max), and, if Δt≦t_(max), to identifythe accumulated time at with said time difference t₂ -t₁ and todetermine said time ΔT₁ by the relation ΔT₁ =(t₂ -t₁ -Δt_(dp))/2. 16.Apparatus according to claim 15, further comprising:a pulse modifiermodule to receive said receiver-amplifier module output signal, to issuean output signal to said end-of-packet detector that is a single pulseof a predetermined voltage v₁₁ and of length equal to a predeterminedtime interval Δt_(p4) if a non-zero input signal is received, and toissue an output signal to said end-of-packet detector that is asubstantially constant, predetermined voltage v₁₂ if no non-zero inputsignal is received.
 17. Apparatus according to claim 16, wherein saidpulse modifier module comprises:first and second signal lines to receiveand propagate said receiver-amplifier module output signal, where thesecond signal line introduces a time delay of predetermined amountΔt_(p4) relative to the first signal line; and first and secondflipflops, each having a data input terminal and a clock input terminal,whose data input terminals are held at high voltages, with the first andsecond signal lines being connected to the clock input terminals of thefirst and second flipflops, respectively, where the Q* output terminalof the second flipflop is connected to the clear input terminal of thefirst flipflop, and the output signal from the Q output terminal of thefirst flipflop is said output signal from said pulse modifier module.18. Apparatus according to claim 16, wherein said end-of-packet detectormodule comprises:a delay line module having an input terminal to receivesaid pulse modifier module output signal and having a plurality of Kconsecutive time delay output terminals where K is a positive integer,and each delay line module reproduces the input signal with apredetermined time delay Δt_(c) relative to the output signal from theimmediately preceding time delay output terminal, where Δt_(c) <Δt_(p4)and KΔt_(c) ≦Δt_(p5) ; logical summing means for the output signals fromdelay line module output terminals, for forming the logical sum of thesesignals and for issuing this logical sum of said output signal as afirst end-of-packet detector module.
 19. Apparatus according to claim18, wherein said end-of-packet detector module further comprises:aflipflop having a clock input terminal that receives said firstend-of-packet detector module output signal; a first monostable vibratorhaving a first input terminal that is connected to the Q output terminalof the flipflop, having second input and clear input terminals that areconnected to a high voltage source, and having a Q* output terminal thatproduces an output signal pulse of predetermined temporal length Δt_(v1)that is received by the clear input terminal of the flipflop; a secondmonostable vibrator having a first input terminal that is grounded,having a second input terminal that is connected to the Q* outputterminal of the first vibrator, and having a clear input terminal thatis connected to a high voltage source, and having a Q* output terminalthat is connected to the preset input terminal of the flipflop and thatproduces an output signal pulse of predetermined temporal length Δt_(v2); where the flipflop has a Q* output terminal that issues a secondend-of-packet detector module output signal.
 20. Apparatus according toclaim 16, wherein said packet activity and counter module comprises:amonostable vibrator having a first input terminal to receive said pulsemodifier module output signal, having second and third input terminalsthat are connected to a high voltage source, having a Q output terminalto issue an output signal pulse of predetermined temporal length Δt_(v)each time a pulse is received at the input terminal, and having a Q*output terminal; a pulse counter having an input terminal connected tothe Q* output terminal of the monostable vibrator and having a clockinput terminal connected to receive said pulse modifier module outputsignal, where the counter has an output terminal that issues a counteroutput signal that is a pulse and resets each time the counter reaches acount K, where K is a predetermined positive integer; and a flipflop,having a flipflop preset terminal and a D input terminal that are heldat a high voltage, having a clock input terminal that receives thecounter output signal, and having a flipflop clear terminal that isconnected to the Q output terminal of the monostable vibrator, where theoutput signal issued by the Q* output terminal of the second flipflop issaid start-of-packet output signal.
 21. Apparatus according to claim 16,further comprising a collision detector that has an input terminalconnected to said second end of said cable, that has an output terminalconnected to an input terminal of said event timer control module, thatproduces an output signal of predetermined voltage V₂₃ if the collisiondetector detects a collision of two or more signals on said cable, andthat produces an output signal of predetermined voltage V₂₄ if thecollision detector does not detect a collision of two or more signals onsaid cable.
 22. A method for determining the position of each of aplurality of broadcasting stations that are connected to and communicatewith each other on a bus topology cable network of such stations bybroadcasting and receiving packets on the cable, where if a packet istransmitted or received by a station, the station does not broadcast apacket during an interframe time interval of predetermined lengthΔt_(gap) that immediately follows transmission or receipt of thepreceding packet, the method comprising the steps of:providing an echomodule, positioned at a first end of a cable, to receive a broadcastpacket, to determine whether the broadcast packet is the last packetreceived before an inter frame time interval and whether at least apredetermined number of broadcast packets have been received, and ifboth these conditions are satisfied to broadcast an echo packet on thecable network after a predetermined time delay Δt_(d), where Δt_(d)<<Δt_(gap) ; providing a processor module, positioned at a second end ofthe cable, to receive a broadcast packet, to determine the time t₁ atwhich the broadcast packet arrives at the processor module, to receivean echo packet signal and to determine the time t₂ at which the echopacket arrives at the processor module, and to determine the timeinterval ΔT₁ required for a packet to travel from the broadcastingstation to the echo module by the relation ΔT₁ =(t₂ -t₁ -Δt_(dp))/2where Δt_(dp) is a net time delay associated with signal processing inthe processor module.
 23. A method for determining the position of eachof a plurality of broadcasting stations that are connected to andcommunicate with each other on a bus topology network of such stations,the method comprising the steps of: providing an echo module, positionedat a first end of a cable, to receive a broadcast packet, to determinewhether the broadcast packet is the last packet received before aninterframe time interval and whether at least a predetermined number ofbroadcast packets have been received, and if both these conditions aresatisfied to broadcast an echo packet on the cable network after apredetermined time delay Δt_(d) ;providing a processor module,positioned at a second end of the cable, to receive a broadcast packet,to determine the time t₁ at which the broadcast packet arrives at theprocessor module, to receive an echo packet signal and to determine thetime t₂ at which the echo packet arrives at the processor module, and todetermine the time interval ΔT₁ required for a packet to travel from thebroadcasting station to the echo module by the relation ΔT₁ =(t₂ -t₁-Δt_(dp))/2 where Δt_(dp) is a net time delay associated with signalprocessing in the processor module.
 24. A method for determining theposition of each of a plurality of broadcasting stations that areconnected to and communicate with each other on a bus topology cablenetwork of such stations by broadcasting and receiving packets on thecable, where if a packet is transmitted or received by a station, thestation does not broadcast a packet during an interframe time intervalof predetermined length Δt_(gap) that immediately follows transmissionor receipt of the preceding packet, the method comprising the stepsof:providing an echo module, positioned at a first end of a cable, toreceive a broadcast packet, to determine whether the broadcast packet isthe last packet received before an inter frame time interval and whetherat least a predetermined number of broadcast packets have been received,and if both these conditions are satisfied to broadcast an echo packeton an echo communication line after a predetermined time delay Δt_(d),where Δt_(d) <<Δt_(gap) ; providing a processor module, positioned at asecond end of the cable, to receive a broadcast packet, to determine thetime t₁, including a time delay Δt_(dp) for identification of an echopacket, at which the broadcast packet arrives at the processor module,to receive an echo packet signal and to determine the time t₂ at whichthe echo packet on the echo communication line arrives at the processormodule, and to determine the time interval ΔT₁ required for a packet totravel from the broadcasting station to the echo module by the relationΔT₁ =(t₂ -t₁ -Δt_(dp))/2 where Δt_(dp) is a net time delay associatedwith signal processing in the processor module; and providing an echocommunication line that is separate from the cable and connects the echomodule and the processor module, to transport an echo packet from theecho module to the processor module.
 25. A method for determining theposition of each of a plurality of broadcasting stations that areconnected to and communicate with each other on a bus topology networkof such stations, the method comprising the steps of:providing an echomodule, positioned at a first end of a cable, to receive a broadcastpacket, to determine whether the broadcast packet is the last packetreceived before an interframe time interval and whether at least apredetermined number of broadcast packets have been received, and ifboth these conditions are satisfied to broadcast an echo packet on anecho communication line after a predetermined time delay; providing aprocessor module, positioned at a second end of the cable, to receive abroadcast packet, to determine the time t₁ at which the broadcast packetarrives at the processor module, to receive an echo packet signal and todetermine the time t₂ at which the echo packet arrives on the echocommunication line at the processor module, and to determine the timeinterval ΔT₁ required for a packet to travel from the broadcastingstation to the echo module by the relation ΔT₁ =(t₂ -t₁ -Δt_(dp))/2where Δt_(dp) is a net time delay associated with signal processing inthe processor module; and providing an echo communication line that isseparate from the cable and connects the echo module and the processormodule, to transport an echo packet from the echo module to theprocessor module.